READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME

摘要

A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and the memory controller. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing memory refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. Both the read buffer and the write buffer can be constructed of DRAM cells.