发明名称 SHARED CACHE STRUCTURE FOR TEMPORAL AND NON-TEMPORAL INSTRUCTIONS
摘要 A method and system for providing cache memory management. The system comprises a main memory (11), a processor coupled to the main memory, and at least one cache memory (50) coupled to the processor for caching of data. The at least one cache memory has at least two cache ways (50), each comprising a plurality of sets (50). Each of the plurality of sets has a bit (50) which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
申请公布号 WO9950752(A9) 申请公布日期 2000.05.25
申请号 WO1999US06501 申请日期 1999.03.24
申请人 INTEL CORPORATION;PALANCA, SALVADOR;COORAY, NIRANJAN, L.;NARANG, ANGAD;PENTKOVSKI, VLADIMIR;TSAI, STEVE 发明人 PALANCA, SALVADOR;COORAY, NIRANJAN, L.;NARANG, ANGAD;PENTKOVSKI, VLADIMIR;TSAI, STEVE
分类号 G06F12/08;G06F12/12;(IPC1-7):G06F12/08 主分类号 G06F12/08
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