发明名称 CIRCUIT FOR DATA DEPENDENT VOLTAGE BIAS LEVEL
摘要 <p>Briefly, in accordance with one embodiment, an integrated circuit (400) includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level (V bias), wherein the circuit further includes the capability (DAC) to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the comparator output signal.</p>
申请公布号 WO2000030261(A1) 申请公布日期 2000.05.25
申请号 US1999026257 申请日期 1999.11.05
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