| 摘要 |
PURPOSE: A dynamic memory apparatus is provided to accelerate the speed of access and cycle and to reduce the chip area of a timing control circuit and the power consumption of a memory chip used in the inner of the memory chip. CONSTITUTION: A DRAM cell circuit(1) comprises a plurality of word lines(SWL) and a plurality of bit line pairs. DRAM memory cells are located on each intersection point of the word lines and the bit lines. One SA circuit(2A) is provided for each bit line pair. The SA circuit(2A) is located symmetrically with respect to the DRAM cell circuit(1) in the upper part and the lower part of the DRAM cell circuit(1). Each record SA part(22) comprises a precharge equalizer(33). A read SA part, comprising a second detection amplifier(28), a read switch(29), a record switch(30) and a precharge equalizer(31), is provided to the record SA parts(22) in common. An SA selection circuit(23), located between the read SA part(24) and the record SA parts, comprises a plurality of transmission gates controlled respectively by transmission gate control signals(TGI-TG4). A couple of input/output terminals of the second detection amplifier(28) are connected to a first bit line pair of the DRAM cell circuit through a first transmission gate pair. A couple of output parts of the read switch(29) controlled by a read signal(RS) are connected to a data input/output circuit(5) through output data line pairs.
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