OFFSET DRAIN FERMI-THRESHOLD FIELD EFFECT TRANSISTORS

摘要

An offset drain Fermi-threshold field effect transistor (Fermi-FET) includes spaced apart source and drain regions in an integrated circuit substrate, an d a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions. A gate insulating layer is on the integrated circuit substrate between the spaced apart source and drain regions, and a gate electrode is on the gate insulating layer. The gate electrode is closer to the source region than to the drain region. Stated differently, the drain region is spaced farther away from the gate electrode than the source region . The offset drain Fermi-FET can introduce a drift region between the drain region and the Fermi-FET channel that can provide the high voltage and/or hi gh frequency Fermi-FETs, while retaining the Fermi-FET advantages in the channe l.