EVALUATING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PURPOSE: An evaluating system for a semiconductor integrated circuit is provided to come onto the market rapidly by evaluating at high speed a test pattern for LSI device generated on the basis of CAD data in the design stage. CONSTITUTION: A test pattern file stores a test pattern applied to a device for testing a device in the course of testing. A first memory stores tester event information by receiving the selected amount of test pattern from the first memory. A first first-in-first-out(FIFO) receives the selected amount of tester event information from the first memory and extracts tester event information for receiving the selected amount of tester event information. A second memory stores device event information by receiving the selected amount of event information obtained from a logic simulation in the course of testing on the basis of design data generated through CAD. A second FIFO receives the selected amount of device event information from the second memory and extracts device event information for receiving the device event information. A comparator compares event information of the first FIFO with event information of the second FIFO. A generator generates the compared results from the comparator.