| 摘要 |
PURPOSE: A system for optimizing a repair time is provided to test integrated circuit or semiconductor memory chips effectively by having identifiers in memory chips. CONSTITUTION: A test device(100) comprises integrated circuits or semiconductor memory chips(140)such as DRAMs, having a plurality of bits or memory cells(120). Each memory chip has a unique identifier, a fuse identifier having a series of selectively blown fuses corresponding to a unique binary number, located on the memory chip. The information contained in the fuse identifier is also stored in a data base(130). Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and the failed test identifier is stored in the database with the associated memory chip identifier. In order to repair the memory chip, failed test data are read out of the database and only selected tests which the chips failed are again performed on the failed memory chip in order to determine which bit in the memory chip is faulty. The failed bits are then repaired by substitution of redundant rows or columns. |
