MEMORY CONTROLLER WHICH INCREASES BUS UTILIZATION BY REORDERING MEMORY REQUESTS

摘要

A scheduler (1006) suitable for reordering of memory requests to achieve higher average utilization of the command (912) and data bus (914) is described. The scheluder (1006) for scheduling a plurality of commands to an associated memory (908), the memory (908) comprising M memory banks and a plurality of N memory pages, includes restriction circuitry (1016) for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuity (1018) for determining an order in which commands should be transmitted to the associated memory (908) with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.