| 摘要 |
PURPOSE: A memory device suitable for double data transfer rate to proceed a record-interrupt-read operation, even in case that read command interrupts the operation of bust record, is provided. CONSTITUTION: A decoder control circuit(18) and a record amplifier control circuit(16) are provided for each memory block and memory bank. A clock(CLK) and a clock enable signal(CKE) are supplied to a clock buffer(30) by an external memory controller. Synchronized with clock(CLK0 degree), a command decoder(32) inputs control signals /CS, /RAS, /CAS and /WE to generate command and decodes them to detect internal condition. A control signal latch circuit(36) provides a record enable signal(WE), a read enable signal(RE), a record clock(CLK-R) for the memory bank according to the detected internal condition decoded by the command decoder(32). An address buffer/register and bank selector(34), synchronized with the clock(CLK0 degree), supplies row and column addresses to the memory bank. A column address counter(40) provides increased column addresses for the memory bank. A parallel/serial converter(42) provides the data outputted by the double data transfer rate to a data output buffer(10).
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