| 摘要 |
PURPOSE: A semiconductor memory device, using four transistor type memory cells equipped with an error writing prevention circuit, is provided to prevent information unnecessary to be written in the memory cell from being written by the line capacitance between adjacent bit lines. CONSTITUTION: An SRAM(100) consists of four transistor type memory cell arrays(1), a column address decoder(3), a row address decoder(4), a bit line control circuit(5), a data input buffer(7), a data output buffer(6), pre charging circuit(8), an address transition detection circuit(9) and an error writing prevention circuit(10). The four transistor type memory cell arrays(1) stores data. The column address decoder(3) outputs a word line selection signal(101) to make data select the required bit lines of memory cell inputted from an address buffer(2). The row address decoder(4) selects the required bit lines. The bit line control circuit(5) reads and writes a required memory cell data. The data input buffer(7) inputs the required memory cell data. The data output buffer(6) outputs the required memory cell data.
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