发明名称 Frequency multiplier capable of taking out efficiently and stably harmonics higher than fourth order
摘要 One end of a first transmission line 3 is connected to the collector of an HBT 2 with the base connected to an output terminal of an input-side matching circuit 1 and with the emitter grounded, and one end of an end-open stub 4 for blocking the passage of the doubled wave is connected to the other end of the first transmission line 3. One end of a second transmission line 5 is connected to the other end of the first transmission line 3, and one end of an end-open stub 6 for blocking the passage of the fundamental wave is connected to the other end of the second transmission line 5. An input terminal of an output-side matching circuit 7 is connected to the other end of the second transmission line 5. The fundamental wave is reflected toward the HBT 2 at the connecting point of the end-open stub 6 for blocking the passage of the fundamental wave, while the doubled wave is reflected toward the HBT 2 at the connecting point of the end-open stub 4 for blocking the passage of the doubled wave, by which only harmonics of quadrupled wave or higher-ordered waves are outputted via the output-side matching circuit 7. Thus, the frequency multiplier is capable of taking out fourth- or higher-ordered harmonics efficiently with a simple constitution using one high frequency transistor, and can be reduced in size and stabilized in operation. <IMAGE>
申请公布号 EP1003277(A1) 申请公布日期 2000.05.24
申请号 EP19990122340 申请日期 1999.11.09
申请人 SHARP KABUSHIKI KAISHA 发明人 YAMADA, ATSUSHI
分类号 H01P1/203;H03B19/14;H04B1/04 主分类号 H01P1/203
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