Processor for information processing equipment and control method

摘要

For improving data efficiency of a bus in a system using address/data multiplex bus, in a processor for information processing equipment, there are provided buffers 31 and 32 being able to store plural sets of write addresses and data for a system bus 800, a compartor 37 for deciding whether the write addresses are continuing or not in access requirements coming before and after about the same time, and means 45 for converting plural write operations for said continuing addresses into a burst transfer protocol which can be transferred with a series of continuing data cycles following one address cycle, when the decision result by the comparator 37 detects ones which come before and after are continuous in the write addresses thereof.