| 摘要 |
<p>A low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in a half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is designed to be used in conjunction with shunt regulators to reject ripple from the power supplies. <IMAGE></p> |
