Flexible placement of GTL end points using double termination points

摘要

A highly parallel computer system including dual processors and dual memory controllers are coupled to an Assisted Gunning Transceiver Logic Plus (AGTL+) high speed system bus. The microprocessors are designed for a quad processor architecture requiring four processors and four connectors for the processors. To maintain signal timing and integrity in a dual processor/dual memory controller architecture, additional terminations are inserted. Printed circuit board space is conserved with a dual processor architecture. The additional connectors and traces to the additional connectors for the processors are no longer needed. Furthermore, with the dual processor design, there is no need for two additional termination cards.