发明名称 |
Combined NMOS and SCR ESD protection device |
摘要 |
A device layout is disclosed for an ESD device for protecting NMOS or Drain-Extended (DENMOS) high power transistors where the protection device (an SCR) and the NMOS or DENMOS transistors are integrated saving on silicon real estate. The integration is made possible by adding a p+ diffusion to the n-well (drain) of a high power NMOS (DENMOS) transistor such that the added p+ diffusion together with the aforementioned n-well and the p-substrate of the silicon wafer create one of the two transistors of the SCR. A low triggering voltage of the SCR is achieved by having the second parasitic npn transistor of the SCR in parallel with the NMOS (DENMOS) transistor by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n+ diffusion (emitter/source) in the p-substrate. A high HBM ESD Passing Voltage is obtained by utilizing the tank oxide method of a DENMOS transistor.
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申请公布号 |
US6066879(A) |
申请公布日期 |
2000.05.23 |
申请号 |
US19990304304 |
申请日期 |
1999.05.03 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LEE, JIAN-HSING;LIU, KUO-CHIO |
分类号 |
H01L27/02;(IPC1-7):H01L23/62 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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