发明名称 |
Method for fabricating a shielded multilevel integrated circuit capacitor |
摘要 |
A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit. The first plate and the third plate are connected to give a total capacitance given by the sum of capacitances between the first plate and second plate and between the second plate and third plate.
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申请公布号 |
US6066537(A) |
申请公布日期 |
2000.05.23 |
申请号 |
US19980017406 |
申请日期 |
1998.02.02 |
申请人 |
TRITECH MICROELECTRONICS, LTD. |
发明人 |
POH, DAVID HO SENG |
分类号 |
H01L21/02;H01L23/522;H01L27/06;(IPC1-7):H01L21/20 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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