| 摘要 |
Redundant memory portions having redundant memory cells for relieving malfunctioning normal memory cells are arranged among the semiconductor memory portions that neighbor each other in the row direction and in the column direction on a semiconductor wafer on which a plurality of semiconductor memory portions are arranged in the form of a matrix. Cutting lines are formed between the redundant memory portions and the neighboring semiconductor memory portions, so that the semiconductor wafer can be separated into semiconductor memory devices (chips) in a subsequent stage in a manner in which the redundant memory portions are connected to the semiconductor memory portion as required. This embodiment makes it possible to decrease the chip size and to efficiently substitute the redundant memory cell array for the defective lines.
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