| 摘要 |
An apparatus employing a cache memory based approach to instruction execution includes a cache memory and one or more control units. The control units operate the cache memory to directly supply appropriate ones of a plurality of values stored in selected ones of said cache locations for a plurality of variables to one or more arithmetic logic units (ALU) as inputs to arithmetic/logic operations, and/or to directly accept and store results of arithmetic logic operations from the one or more ALU as values of the variables in selected ones of said cache locations. The direct supplying and the direct accepting and storing are performed responsive to instructions specifying said arithmetic/logic operations and logically designating the variables associated with the specified arithmetic/logic operations. |
