| 摘要 |
A bi-phase, single-wire dynamic bus for allowing communication during either of a first phase or a second phase of a clock signal is presented. A data signal that is to be written onto a single bus wire is written onto the bus, via a write enable circuit, during one of the first or second clock phase. A precharger circuit precharges the bus on the subsequent clock phase, which is the other of the first or second clock phase.
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