发明名称 Column redundancy circuit with reduced signal path delay
摘要 A semiconductor memory has memory elements arranged in memory blocks with each memory block having normal columns and at least one redundant column. In the event of a normal column being found to be defective, a redundant column may be used to replace the defective column. The semiconductor memory allows a redundant column in one block to replace a defective column in another block. The memory block may also be separated into an upper and lower portion allowing the portions to individually replace upper or lower column portions from different defective columns.
申请公布号 AU1024500(A) 申请公布日期 2000.05.22
申请号 AU20000010245 申请日期 1999.10.29
申请人 MOSAID TECHNOLOGIES INCORPORATED;MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 FANGXING WEI;HIROHITO KIKUKAWA;CYNTHIA MAR
分类号 G11C11/401;G06F11/20;G11C29/00;G11C29/04 主分类号 G11C11/401
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