发明名称 DYNAMIC REGISTER WITH LOW CLOCK RATE TESTING CAPABILITY
摘要 <p>A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the ouput terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.</p>
申请公布号 WO2000028341(A2) 申请公布日期 2000.05.18
申请号 US1999026482 申请日期 1999.11.09
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