Data prefetch apparatus and method

摘要

A load target circuit (56) with a plurality of entries (561). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.