| 摘要 |
<p>Disclosed is a timing circuit which produces control signals by which a data interfacing section can simultaneously implement input and output operations of a video data from a frame memory and to an address electrode driving section, respectively. A first pulse signal whose pulse duration corresponds to a whole horizontal line time, a second pulse signal which is identical to a delayed first pulse signal by one horizontal line time and a third pulse signal whose pulse duration is the one horizontal line time longer than that of the first pulse signal are produced by using a system clock signal of 2 MHz. During the pulse duration of the third pulse signal, a first clock signal which contains pulse signals whose numbers are one number larger than the numbers of whole horizontal lines (480) by using a system clock signal of 25 MHz. The first clock signal is provided to the data interfacing section to control the input and output operations thereof. A clock signal including 480 numbers of pulses obtained from a logical multiplication of the first clock signal and the first pulse signal is used for a control of an output operation of the frame memory. Another clock signal, which is delayed by the one horizontal line time, including 480 numbers of pulses obtained from a logical multiplication of the first clock signal and the second pulse signal is used for a control of an input operation of the address electrode driving section.</p> |
