| 摘要 |
For use in an x-86 processor having a physically-addressable cache and an associated translation look-aside buffer (primary TLB) that stores corresponding logical and physical addresses for addressing the cache, a circuit for increasing a retrieval speed of a line from the cache. In one embodiment, the circuit comprises: 1) a TLB slice, located proximate the cache, that contains copies of portions of the physical addresses stored in the primary TLB and returns one of the portions as a function of a portion of a logical address supplied thereto; and 2) a decoder, coupled to the TLB slice, that decodes the one of the portions to yield multiplexer selection signals, the TLB slice and the decoder cooperating to increase the retrieval speed by avoiding logic circuitry interposed between the primary TLB and the cache.
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