| 摘要 |
A non-volatile semiconductor storage device 100 comprised of a bit number detection circuit 120. The bit number detection circuit 120 has a counting circuit 604, a division control circuit 606 and a latch circuit 602. The counting circuit 604 counts the number of memory cells targeted for data writing. The division control circuit 606 specifies four memory cells for simultaneous data writing on the basis of a count value. The latch circuits 602 expect the circuits corresponding to the specified memory cells are reset for data writing prohibition.
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