发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device which can be protected against the occurrence of latch-ups after power is applied. SOLUTION: This semiconductor device operates in such a manner that transistors MN1, MN2, MP1, and MP2 are operated under the control of a reset circuit 14 until sufficient time elapses after a power supply is applied, including a time from a point of time when a power supply VDD2 is applied to another time when a power supply VDD1 is applied, an N well 11 is connected to a power supply voltage VDD2 terminal, and a P well 12 is connected to a ground potential VSS terminal. With this setup, a substrate potential can be restrained from falling into a floating state so as not to cause a latch-up. After a prescribed time has elapsed, the transistors MN1, MN2, MP1, and MP2 are all turned off under the control of the reset circuit 14, and a bias voltage is applied to the N well 11 and the P well 12 corresponding to their polarity.
申请公布号 JP2000138348(A) 申请公布日期 2000.05.16
申请号 JP19990235642 申请日期 1999.08.23
申请人 TOSHIBA CORP 发明人 HATORI FUMITOSHI;FUJITA TETSUYA
分类号 G11C11/413;G11C11/408;H01L21/822;H01L27/04;H03K19/003;(IPC1-7):H01L27/04 主分类号 G11C11/413
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