发明名称 TEST METHOD OF EMBEDDED CORE IN SYSTEM-ON-CHIP AND CONSTITUTION THEREOF
摘要 PROBLEM TO BE SOLVED: To make a test possible without particularly increasing the hardware of a system-on-chip IC by constituting the device by providing a plurality of registers for testing microprocessor cores in IC chips. SOLUTION: In the test of a system-on-chip IC, a microprocessor core is at first tested, a memory test signal pattern is generated by utilizing the computing ability, the test pattern is given to an embedded memory core, and by evaluating the response signal of the memory, existence of inferiority is verified. The test of the microprocessor is made possible, for example by adding three resisters TCR 22, LFSR 24, MISR 26 and two multiplexers 32, 34 to the microprocessor. The register TCR 22 supplies an operation code of instruction in a test mode, and the LFSR 24 generates the operand for instruction. The computed result from an execution unit 15 is stored in the MISR 26.
申请公布号 JP2000137061(A) 申请公布日期 2000.05.16
申请号 JP19990304327 申请日期 1999.10.26
申请人 ADVANTEST CORP 发明人 ROCHETTO RAJUMAN;YAMOTO HIROAKI
分类号 G06F11/22;G01R31/28;G01R31/3183;G01R31/3185;G06F11/267;G11C29/20 主分类号 G06F11/22
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