| 摘要 |
PROBLEM TO BE SOLVED: To prevent the occurrence of a glitch in the clock signal output, when switched, in a device which selectively outputs two asynchronous clock signal inputs. SOLUTION: A clock signal switching device selects an outputted clock signal (CLKA or CLKB) based on a selected signal SEL, but, since the switching timing is controlled by a handshake signal (SELA or SELB) synchronized to each clock signal, the selection is not interrupted in the course of a pulse. When, for example, the clock signal is switched from CLKA to CLKB, the handshake signal SELA disables the CLKA of a terminal 20 at an AND gate 56. In addition, the other handshake signal SELB does not become 'high' until the signal SELA becomes 'low' (indicating that the clock signal CLKA is disabled) and the handshake signal CLKB at the input 28 of another AND gate 58 is not outputted. Since the handshake signal SELB is also synchronized to the clock signal CLKB, the signal CLKB is not outputted from the gate 58 in the course of a pulse.
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