| 摘要 |
The present invention is generally directed to a multi-mode buffer that is configurable to control output delivered to an input, with a variable clock cycle delay. For example, the buffer may be controlled, in one mode to deliver input data to an output, at a one clock cycle delay (i.e., output data at next clock edge). In another mode, the buffer may be controlled to deliver input data to an output, at a two clock cycle delay. In accordance with one aspect of the present invention, the buffer includes a clock input, a data input, a control input, and an output. The input and the output may be of variable bit width. For example, 8 bits, 16 bits, or some other bit width. The buffer further includes circuitry for delivering data on the data input to the output in response to the clock input. In this regard, the buffer includes circuitry responsive to the control input to vary a delay in delivering the data input to the output, such that the delay may be one clock cycle, two clock cycles, or some other desired length.
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