| 摘要 |
A semiconductor device comprising a substrate having thereon an active area including a plurality of MOS transistors, an inactive area, and adjacent gate wires having walls and a sidewall on the walls of the gate wires. The adjacent gate wires are arranged on the active area and on the inactive area. A first interval between the adjacent gate wires on the active area is greater than a second interval between the adjacent gate wires on the inactive area. The active area includes one of a source and drain region formed by introducing an impurity in an interval between the adjacent gate wires. This structure circumvents the problem which would otherwise occur when the active area between the adjacent gate wires is covered by the sidewalls to thereby block ion implantation. Also, the overall size of the semiconductor device can be reduced and the wiring density can be increased. The gate wiring interval in the portion in which a transistor is formed is a minimum interval needed to provide an opening that is not blocked by the sidewalls. At the same time, the minimum interval realizable by patterning technology is applied to the interval between the gate wires when used as signal wires on the inactive area.
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