Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits

摘要

A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750 DEG C. and 850 DEG C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.