发明名称 FAIL DATA MEMORY CIRCUIT FOR SEMICONDUCTOR TESTING DEVICE
摘要 PROBLEM TO BE SOLVED: To simplify the structure of a circuit by comparing a data output from a device to be measured with an expected data pattern, making determination, temporarily storing the data and the result of the determination according to address data when the result of the determination is entered, and generating an output clock signal based on an output request signal. SOLUTION: As a writing pattern supplied to a device 4 to be measured, a pattern generator 3 outputs a writing pattern A to a driver circuit 2, and a comparator 5 outputs the expected pattern of fail determination time. The driver circuit 2 generates a writing pattern B to be supplied to the device 4 to be measured based on the entered writing pattern A, generates an address B to be accessed, and outputs this to the device 4 to be measured. The comparator 5 compares the data output of the device 4 to be measured with the expected pattern supplied from the pattern generator 3, and outputs determination result data A when there is fail data.
申请公布号 JP2000137997(A) 申请公布日期 2000.05.16
申请号 JP19980310260 申请日期 1998.10.30
申请人 ANDO ELECTRIC CO LTD 发明人 TANABE KEIJI
分类号 G01R31/28;G06F1/04;G11C29/00;(IPC1-7):G11C29/00 主分类号 G01R31/28
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