| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device obtaining high data transfer efficiency in all cases of at the time of continuous read-out operation, at the time of continuous write-in operation and at the time of continuous read-out/write-in operation. SOLUTION: When a read latency (R.L.) from setting of a read-out command (RCMD#1) until the read-out data (#1) are defined and a write latency (W.L.) from the setting of a write-in command (WCMD#1) until the effective data (#1) are awaited are set in the same clock cycle value (=3), the timing of an access operation start to a memory cell is changed each other by (3 CLOCK CYCLES) in the read-out operation and the write-in operation.</p> |
