| 摘要 |
PCT No. PCT/JP95/02744 Sec. 371 Date Jun. 23, 1997 Sec. 102(e) Date Jun. 23, 1997 PCT Filed Dec. 28, 1995 PCT Pub. No. WO97/24622 PCT Pub. Date Oct. 7, 1997An I/O pin electronics circuit for semiconductor test system to perform an I/O common test as well as an I/O separate device test without causing unused circuit in a comparison circuit, a comparison voltage generation circuit, a wave formatter circuit and a supply voltage generation circuit and without decreasing the number of devices that can be simultaneously tested, for high speed devices where an I/O dead band poses a problem. The I/O pin electronics circuit includes a pair of drivers which are commonly connected to a supply/termination voltage generation circuit and a wave formatter circuit, and a comparator having a comparison circuit and a comparison voltage generation circuit is connected to one of the drivers. |
