| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control circuit reduced in power consumption and capable of preventing a logical indefinite state in a high impedance state while automatically identifying the classification of a memory. SOLUTION: A switch element 13a is provided between a bus hold circuit 13 and a memory bus 15, and the switch element 13a is turned off so that the bus hold circuit 13 can be invalidated during the execution period of a memory automatic identification sequence, and the switch is turned on so that the bus hold circuit can be validated in the other period (in a normal operation) by a means 14 such as a register for indicating that the automatic identification sequence is being executed. Also, the output of the bus hold circuit 13 can be constituted of a 3State output instead of the switch element. Also, the bus hold circuit 13 can be incorporated in a memory element, and incorporated in a memory controller element.
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