| 摘要 |
In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. The dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. As each instruction is dispatched for execution from the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution. In this manner, an out-of-order processing scheme is implemented that efficiently accounts for data dependency between processed instructions. |
