CELL STRUCTURE FOR FERROELECTRIC MEMORY CELL

摘要

PURPOSE: A cell structure for ferroelectric memory cell is provided to improve a velocity and a reliability by performing a high data sensing operation and a re-storing operation to prevent a data loss. CONSTITUTION: First and second MOS transistors(N0,N1) are interconnected in serial between two bit lines(BL0,BL1). Gates of first and second MOS transistor(N0,N1) are connected to a word line(WL). A third MOS transistor(N3) is connected between first and second MOS transistors(N0,N1) and plate lines(PL). Gate of the third MOS transistor(N3) is connected to the word line(WL). A source of the first MOS transistor(N0) is connected to a upper electrode of a first ferroelectric capacitor(X0). A source of the second MOS transistor(N1) is connected to a upper electrode of a second ferroelectric capacitor(X1). Lower electrodes of the first ferroelectric capacitor(X0) and the second ferroelectric capacitor(X1) are interconnected and connected to a drain of the third MOS transistor(N3). A source of the third MOS transistor(N3) is connected to the plate line(PL).