| 摘要 |
PURPOSE: A serial Reed-Solomon decoder is provided to reduce a chip size by causing the decoder to synchronize with a bit clock. CONSTITUTION: The serial Reed-Solomon decoder includes a syndrome computation part for computing a syndrome polynomial of an inputted code data. An error position and correction polynominal computation part computes an error value polynomial and an error position value polynomial using the syndrome polynomial. The syndrome computation part includes a demultiplexer(31), a computation part(32a,32b,33a,33b,34a,34b,35a,35b36a,36b), and a delay part(37a,37b). The demultiplexer(31) demultiplexes the inputted code data for determining whether an inputting order of the inputted code data is either odd or even. The computation part(32a,32b,33a,33b,34a,34b,35a,35b36a,36b) adds a coefficient value to an output of the demultiplexer. The delay part(37a,37b) delays an added value outputted from the computation part to synchronize the added value with the bit clock and provides a delayed value to the computation part(32a,32b,33a,33b,34a,34b,35a,35b36a,36b).
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