PURPOSE: A test register circuit is provided to reduce a test operation time by setting a test mode for analyzing a chip characteristic and simultaneously performing a read operation of a test register during the operation of the test mode. CONSTITUTION: A first transmission gate circuit(11) provides a data provided through a data input terminal(SHIFTIN) to a first node(K11) according to an input of a clock signal(CLK). A first latch circuit(13) inverts a data of the first node(K11) and provides the inverted data to a second node(K12). A second transmission circuit(12) provides a data of a second node(K12) to a third node(K13) according to an input of an inverted clock signal(CLKb). A second latch circuit(14) inverts a data of the third node(K13) and outputs the inverted data through a data output terminal(SHIFTOUT). A third transmission circuit(15) provides a data outputted through the data output terminal(SHIFTOUT) to a fourth node(K14). A third latch circuit(17) inverts a data of the fourth node(K14) and provides the inverted data to one input of an NOR gate(NOR1).
