CIRCUIT FOR DETECTING ADDRESS TRANSITION

摘要

PURPOSE: A circuit for detecting address transition is provided to decrease a chip size by composing the circuit as one combining circuit unit and one delay circuit unit to a plurality of detecting circuit unit. CONSTITUTION: Output signals of detecting circuits are inputted to a gate of a plurality of PMOS transistors(P11-P1n). A plurality of PMOS transistors(P11-P1n) is connected between a power terminal and an output node(Q11). The power terminal is connected to a gate of a first NMOS transistor(N11). The first NMOS transistor(N11) is connected between the output node(Q11) and a ground terminal(Vss). A resistor(R11) is connected between the first NMOS transistor(N11) and the ground terminal(Vss). An output signal of an inverter(I11) for inverting a potential of a second NMOS transistor(N12) is inputted to a gate of the second NMOS transistor(N12). The second NMOS transistor(N12) is connected between the output node(Q11) and the ground terminal(Vss).