| 摘要 |
PURPOSE: A circuit for multiplying clock frequency is provided to selectively multiply frequency of input clock signal. CONSTITUTION: A circuit comprises 4 circuits. The first circuit generates a 1st and 2nd control signals according to a 1st clock and a 2nd clock delayed to the 1st clock. The second circuit generates a 2nd clock according to the 1st and 2nd control signals, and extracts each pulse signal from each period of the 1st clock. The third circuit generates a 3rd clock by synthesizing the pulse signals. The fourth circuit divides frequency of the 3rd clock. Thereby, the delay time is regulated by feedback of phase-difference between the input clock and the delayed clock, so that the clock frequency can be multiplied as a selected integer ratio.
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