| 摘要 |
PURPOSE: A digital phase locked loop circuit is provided to maintain a synchronized state of a communication apparatus by generating a system clock without regard to a variation of input clock. CONSTITUTION: The digital phase locked loop circuit includes a reference clock detecting/selecting part(11) and a digital phase detecting part(12). The digital phase detecting part(12) divides a clock signal and detects a phase of a clock signal generated from a system clock generating/providing part(18). A mode converter(13) selects one of a free-run mode, a fast mode, a locking mode and a hold-over mode based on the phase detected by the digital phase detecting part(12) and outputs the selected mode to a phase controller(15). The phase controller(15) calculates a mode control value based on a mode information from the mode converter(13) and provides the calculated value to a digital/analog converter(16).
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