TEST CIRCUIT WITH POWER ON RESET CIRCUIT

摘要

PURPOSE: A test circuit is provided to test an inner circuit and a power on reset circuit regardless of an operating voltage. CONSTITUTION: A power on reset circuit(10) generates a reset signal after a source voltage(VCC) is applied to the circuit and reaching the source voltage in some level to reset an inner circuit. An AND gate(21) in a test signal generation circuit(20) receives and mixes high level test signals(TEST, TESTB) and generates a first mixed signal of a high level(COM1). An OR gate(23) admits and mixes the first mixed signal of a high level and a low level reset signal converted by an inverter(22) and generates a second signal of a high level(COM2). An inverter(24) inverts the second mixed signal of a high level to low level signal. An AND gate(25) mixes the second mixed signal of a low level and a high level reset signal(RESET') and makes a high level test signal(TEST') for testing the inner circuit regardless the output of the power on reset circuit(10). In case of testing the output of the power on reset circuit(10), the test signal generating circuit generates a low level test signal(TEST').