| 摘要 |
PURPOSE: A ferroelectric memory device is provided to improve the reliability of a data sensing operation by arranging reference cell blocks with memory cell blocks in a core region and forming each reference having an equal size and structure with each memory cell. CONSTITUTION: A current path of each transistor(60,61,60',61') in bit line precharge blocks(302,302') is connected between a corresponding bit line(BL_0T, BL_1T,BL_0B, or BL_1B) and a ground voltage. Gates of upper transistors(60,61) are an upper bit line precharge control line(BLPR_T) in common. Gates of lower transistors(60',61') are connected to a lower bit line precharge control line(BLPR_B) in common. A current path of each transistor(62,63,62',63') in reference data pass blocks(304,304') is connected to a corresponding bit line(BL_0T, BL_1T,BL_0B, or BL_1B) and a corresponding data line(RFDIN_T or RFDIN_B). Gates of upper transistors(62,63) is connected to a control line(RPS_T) in common and gates of lower transistors(62'63') are connected to the control line(RPS_B) in common.
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