| 摘要 |
PURPOSE: A line buffer controller in a dynamic RAM interface apparatus of a PDP television is provided to normally record and read data by setting an access time and a cycle time using a line buffer in the front of a DRAM. CONSTITUTION: A recording unit(170A) of a line buffer control unit(170) inputs signals relevant to a write clock, a horizontal synchronous signal and valid data. The recording unit(170A) outputs a write reset signal through the second output port(171), and initializes the line buffer unit. The recording unit(170A) applies a write enable signal through the third output port(173) and a write clock through the first output port(171). Data relevant to video data are recorded by a control signal applied from the recording unit(170A). A reading unit(170B) inputs a read enable signal and a horizontal synchronous signal, and applies a write reset signal to the line buffer unit through the second output port(175). The reading unit(170B) applies a read enable signal through the third output port(176), and outputs a read clock to the line buffer unit through the first output port(174).
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