| 摘要 |
<p>PURPOSE:To obtain a voltage step-up circuit without reducing the step-up efficiency even if a multistage connection is performed. CONSTITUTION:A first transistor array A comprising a plurality of MOS transistors T1A and T2A and a second transistor array B comprising MOS transistors T18 and T2B with the same number of transistors as the first transistor array A are provided, and capacitors C1A, C2A, C1B and C2B are respectively connected between each node N1A, N2A, N1B and N2B of the transistor arrays A and B and two phase clock power sources phi1 and phi2 of a non-overlap. Further, while gates of each MOS transistor T1A and T2A of which the first transistor array A is formed are connected to each node N1B and N2B of the second transistor array B, gates of each MOS transistor T1B and T2B of which the second transistor array B is formed are connected to each node N1A and N2A of the first transistor array A.</p> |
