| 摘要 |
PROBLEM TO BE SOLVED: To considerably reduce the total number of delays of one pipeline cycle when there is a condition branch instruction in a repetitive instruction, thus efficiently executing an instruction. SOLUTION: An instruction is decoded in the first half of a decoding stage and it is judged whether it is a branch instruction or not. When it is the branch instruction, an offset contained in the branch instruction is referred to and the realization/non-realization of branch are predicted by the highest bit of the offset. When branch realization is predicted, a value obtained by shifting the offset to left by two bits and extending a code is added to the value of a program counter and a branch destination address is calculated. When the non-realization of branch is predicted, '4' is added to the value of the program counter and real branch realization/non-realization are judged in an execution stage. When predicted branch realization/branch non-realization are correct, the instruction is continued by using the value of the program counter, which is calculated in the decoding stage. When they are not correct, the value of the program counter is returned to the original one and the address is calculated again.
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