发明名称 PLL MODULE AND PORTABLE TERMINAL DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce comparison frequency noise leakage from a PLL-IC and to improve operation stability by performing flip chip mounting of a PLL circuit component on a circuit board as a PLL-IC bare chip. SOLUTION: A PLL-IC bare chip 2 is subjected to flip chip mounting on a circuit board 1 through lands 3a and 3b for connection on the rear face of the bare chip 2 and lands 4a and 4b on the circuit board 1. A signal oscillated from a VCO 6 is outputted externally as an output signal and on the other hand, it is inputted to the bare chip 2 as a feedback signal. And, in a phase comparator in the bare chip 2, the phase difference between the feedback signal having a specific frequency and a reference signal is detected and is outputted to a charge pump circuit, and a control signal is generated so as to perform phase synchronization. A noise component is removed from the control signal through a low pass filter 5 and then, it is feedbacked to the VCO 6.
申请公布号 JP2000134095(A) 申请公布日期 2000.05.12
申请号 JP19980306935 申请日期 1998.10.28
申请人 MURATA MFG CO LTD 发明人 NAKAYAMA NAOKI;HIROTA KOJIRO
分类号 H03B1/04;H03L7/08;H03L7/18 主分类号 H03B1/04
代理机构 代理人
主权项
地址