| 摘要 |
PROBLEM TO BE SOLVED: To speed up a memory and reduce a consumption power by setting a first and a second switches which are turned on and off between an invertor output and a bit line in accordance with a signal on a word line and, a third and a fourth switches which are turned on and off between the bit line and a bit match node in accordance with an invertor output signal. SOLUTION: A voltage amplitude of a word match line 20 is restricted in a range between a higher potential by a threshold voltage of a PMOS transistor with a back gate bias from a ground potential and a lower potential by a threshold of an NMOS transistor NC: 41 with a back gate bias from a power source potential. The range can be made smaller. Accordingly, the voltage amplitude of the word match line 20 becomes small and a consumption power is reduced. When a precharge potential of the word match line 20 is lowered, boosting a bit line is eliminated although the NMOS transistor is used and a high-speed performance is ensured.
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