| 摘要 |
PROBLEM TO BE SOLVED: To obtain a tentative hold circuit that is not malfunctioned even when an input data signal is delayed. SOLUTION: A flip-flop FF 5 receives a monitor period signal FP at its data input terminal and an output (c) resulting from inverting a reference clock signal CLK inverted at an inverter 4 at its clock terminal. A tentative FF 1 receives an output (b) resulting from ANDing a tentative hold signal ERR, and the inverted clock signal (c) at an AND gate 3 at its set terminal, an 'L' level at its data input terminal and an output (d) of the FF 5 at its clock terminal respectively. An output FF 2 receives an output (a) of the FF 1 at its data input terminal and a signal FP at its clock terminal and outputs a monitor result signal ALM from its output terminal.
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